Aditya Vasisht

Background

About Aditya Vasisht

SoC System Performance & Architecture | Pre-Silicon Sign-off | GenAI, XR & AutomotiveI am a SoC System Performance and Architecture Engineer with 13+ years of experience trusted with pre-silicon performance sign-off, architectural trade-off analysis, and silicon risk reduction across GenAI, mobile, XR, modem, and automotive SoCs. I specialize in system-level performance risk assessment, including evaluation of QoS strategies, memory/interconnect behavior, and bottleneck resolution under realistic workloads.At Qualcomm, I operate at system and architecture level, defining workload-driven performance assessment strategies, pioneering emulation-based measurement methodologies, and driving memory and NoC architecture evaluations to enable confident tape-out decisions. My work has been adopted across 20+ successful SoC tapeouts, directly influencing performance readiness and minimizing post-silicon surprises.Previously at Intel, I worked on platform-level power and performance validation for client AI systems, including early MLPerf bring-up and accelerator differentiation, collaborating closely with compiler and software teams across multiple generations.I have worked across the hardware–software boundary on AI and system performance, collaborating with architecture, compiler, and software teams to translate performance insights into design decisions.