Adwait Joshi

Background

About Adwait Joshi

Hardware Validation and Field Application Engineer with 6+ years of experience in USB-IF compliance, signal integrity, and post-silicon validation across USB 2.0/3.2/PD3.2/USB4. Adept at PHY-to-protocol layer testing using high-bandwidth oscilloscopes, BERTs, VNA, and protocol analyzers. Proficient in Verilog, Python, and UVM, with hands-on experience automating validation workflows for Host Silicon, PD devices, and MFi certification. Proven ability to interface with customers throughout the project lifecycle—consulting on SoW definition, component selection, custom test strategies, interpreting specifications, system-level debugging, and managing certification or waiver processes. TECHNICAL SKILLS: Synthesis/Verification and Validation, Static Timing Analysis, RTL Design & Verification, FSM, SV Assertions, Covergroups, MIPS, NIOS2, Pipelining, DFT, BIST, Constraint Random Verification, SOC Design & Verification, Power Verification, FPGA, Machine Learning, Functional Verification EDA TOOLS: Synopsys VCS, Synopsys Design Vision, Synopsys Design Compiler, GTKWave, Cadence Virtuoso, NCVerilog, MATLAB CODING LANGUAGES: Verilog HDL, System Verilog, UVM, Python, C RELEVANT COURSES: ASIC CMOS Design, Advanced Computer Architecture, Digital System Design and Synthesis, SOC Design with System Verilog, Verification with System Verilog and UVM, Linear System Theory, Semiconductor Devices I, CMOS Digital Circuits OS: Windows, Linux PROTOCOLS: AMBA APB, AHB, I2C, SPI, USB 2.0(Basics), PCIe(Basics) LAB TOOLS: Oscilloscopes, Multimeters, Logic Analyzers, DSO, Frequency Generators, Protocol Analyzers, Industry standard test fixtures.