Akansh Agarwal
Cpu Design Verification Engineer at Cadence
Based in Noida, India
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Seniority
Staff
Department
Engineering
Location
Noida
Industry
Software Development
Company size
12K
Contact information
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a•••••••@cadence.com
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5 credits+91 ••• •••• ••••
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Background
About Akansh Agarwal
Working as a CPU design verification of RISCV processors. I have in-depth knowledge of system verilog and UVM. I worked on various blocks of CPU like caches (L1 I-cache, L1 D-cache, L2 cache, L3 cache), Memory Management Unit (MMU), and buses. I worked on AXI protocol also. I worked on setting the verification environment for the blocks mentioned above like the drivers, interfaces files etc. I have good debugging skills. I worked on various tools like vmanager, xcelium, simvision, etc.
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