Amit Dudeja

Smts Design Engineer Manager at Amd

Based in Hyderabad, India

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Seniority

Other

Department

Other

Location

Hyderabad

Industry

Semiconductor Manufacturing

Company size

48K

Contact information

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Email

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a•••••••@amd.com

Phone

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+91 ••• •••• ••••

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Background

About Amit Dudeja

Around 16 years of rich experience in Semiconductor, EDA and Software industries, majorly in the domain of System Level (ESL) design, development and verification.Having experience of performance and power modeling for architecture exploration use case using SystemC and TLM2.0. Also worked on AI workload modelling for architectural exploration.Built and leading the team of engineers working on SystemC simulation flows of AMD FPGA. System Standard: SystemC/TLM2.0Programming Languages : C, C++, Data Structures & AlgorithmsHardware Description Languages: Verilog, VHDL, SystemVerilog Verification Methodology: UVMScripting Language: Tcl, Power Standard: UPF3.0Bus Protocols: HBM,DDR,LPDDR,AXI, Tensilica PIF Protocol Tools: Synopsys PA tools for architecture exploration (PA-MCO & PA-Ultra), TLMC,Xilinx Vivado

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