Ananya Devraj

Background

About Ananya Devraj

RTL designing. Perform micro/hardware architecture & logic design creation for features to be added. RTL designing - Register implementation, integration, solving lint errors BMAN/SIMBUILD flow Python scripting - automation : tool flow and content & test creation. Design and implement of RTL DFD / Design for Debug feature logic for ASIC sub-systems. Update existing design and integrate manually/using various intel tools like Collage, Chef, Connit etc. Collaborate with the physical design team for deciding multi cycle path / pipeline stages addition based on the timing results and then perform timing fixes as necessary. Collaborate with the physical design team for physical design based rule checks, review and perform its fixes as necessary. RTL design changes for adding LCP's, regional and local clock buffer [RCB/LCB] logic using macros. Synthesize and Pre-physical netlist LEC check using conformal tool to make sure about the logical equivalence of written code versus synthesized code. Fixing of metastable conditions due to clock domain crossing [CDC] using synchronizers - manually written sync ckts / macros. Defining multi clock cycle paths. Understanding of verification flow: Execution of test-cases through Trex command & its modification. Can handle VCS, VERDI. Knowledge on DDR SDRAM’s FPGA Implementation using Verilog FPGA Implementation and debugging skills at Board level and system level using Xilinx Tools, Agilent signal generator & analyser and various lab tools. Exposure on DSP filter and DSP implementation on FPGA using Verilog Knowledge on handling MATLAB, SIMULINK & System Generator designs along with behavioural simulations Knowledge on error correcting code Knowledge on Hardware bring-up procedures Exposure on revision control system like Git, BitKeepker and various turn-in ways Knowledge on Perl, C & AES & RSA cryptography Basic knowledge on handling WireShark Network Analyser Excellent analytical, troubleshooting and problem-solving skills