Arjun Gill
Hardware Design Engineer at Intel Corporation
Based in San Francisco, United States
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Seniority
Staff
Department
Engineering
Location
San Francisco
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
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a•••••••@intel.com
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Background
About Arjun Gill
I have been working on DFT related tasks since 2008, across multiple organizations, and have experience on- ATPG using industry standard tools- DFT Verification, Spyglass DFT - Silicon bring up and debug, closure of silicon issues by interfacing across multiple teams - Volume Diagnostics and yield improvement - Test Time and Power reduction methodologies - RTL implementation of DFT architectures for Scan Compression, memory BIST, DFT control block, and JTAG - Verilog/VHDL simulator tool experience. Debugging ATPG/JTAG/BIST vectors using simulation as well as silicon debug- Supplemental test vectors for Low Power Test, Small Delay Defects, Logic Retention and Characterization - Automation/Tools development using C/C++/Perl/TCL/Shell scripting
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