Arshad N.

Background

About Arshad N.

Custom Digital & Mixed-Signal Circuit Design Designed performance/power/area critical custom digital macros. Implemented critical processor memory interface with multi-level Translation Lookaside Buffer (TLBs), its complex TCAM arrays, dynamic encoders, decoders, SRAM circuits. High performance, wire limited multi-ported Register-File circuits. Place & Route of SoC type blocks: Re-architected microArch/behave-RTL, detailed from-scratch floorplan, wire-plan producing highly optimized ckts. Solved challenging critical timing paths pre and post silicon. Designed in: 90/65/45/32/28 & 14/7nm Finfet technology nodes Superconducting Reciprocal Quantum Logic (RQL) circuits: Implemented MCMs driver-transmission-line-receiver circuits, elementary memory arrays, characterized complex library elements with test-beds. Designed RQL-technology test-chips, RQL-ckts using alternating-multi-phase clocks with Mixed Signal Design & Verif. Tools. Debugging difficult circuit timing issues in old Aerospace Electronic circuits. Proposing and implementing circuit fixes in very constrained Design & Timing windows Directed voluntary Non-Profit Work.