Ashish Deshpande

Background

About Ashish Deshpande

20+ years of experience in Functional Verification with exposure to working on various designs such as IPs TestChips SOCs Chiplets and Microcontroller etc. Currently focused on functional verification of complex SoC and Chiplet designs with multi core RISC-V and ARM processors with AI engines and several other complex subsystems such as Video Engines GPU UCIe PCIe Ethernet HBM and LPDDR/DDR. Successfully taped out multiple AI enabled SoCs working swimmingly on silicon and are first pass success which are going for production. Extensive experience in managing multiple projects at the same time with varied team sizes and a mix of FTE PTE and 3rd party contract work. Worked on various industry standard protocols such as Hyper Transport PCIe CXL Ethernet UCIe AMBA etc. for functional verification of these IPs. Also worked on verification of various memory PHY such as DDR LPDDR along with proprietary memory standards like XDR2. Extensive experience in IP verification of SERDES and Memory PHY controller designs and support IPs for Cryptography cores. Extensive experience in building verification environment using industry standard methodologies such as OVM and UVM. Proficient in System Verilog (SV) and Verilog languages. Verification lead for all the Serdes Testchip developed in Rambus with more than 15 chips taped out successfully. Worked on various aspects of verification like test plan creation writing assertions coverage co-sim etc.