Ashish Saini
Senior Design Verification Engineer at L&t Technology Services
Based in Mysore, India
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Seniority
Staff
Department
Engineering
Location
Mysore
Industry
Engineering Services
Company size
40K
Contact information
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a•••••••@ltts.com
Phone
5 credits+91 ••• •••• ••••
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Background
About Ashish Saini
VLSI Domain Skills HDLs: Verilog HVL: System Verilog TB Methodology: UVM Scripting Language: TCL, Linux Others: GLS, UPF EDA Tool: QuestaSim, Modelsim Protocols: AMBA-AXI, AHB Domain: Functional Verification -verification using SV/UVM based verification environment-Experience in writing assertions and functional coverage
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