Ashwinkumar Sivakumar

Background

About Ashwinkumar Sivakumar

With a Master of Science in Electrical and Computer Engineering currently underway at Portland State University, specializing in Design Verification, I bring a comprehensive background in hardware design and verification. Leveraging over two years of experience as an ASIC Verification Engineer at Mbit Wireless and an internship at Sion Semiconductors, I have honed my skills in functional verification, testbench development, and protocol implementation. My primary focus lies in the implementation of the Async FIFO project using UVM, which emphasizes assertions, coverage, and comprehensive testbench development. Additionally, I have spearheaded projects such as DDR-5 memory controller implementation in System Verilog with Python-scripted regression testing, and RISC-V single-cycle processor design and verification using Python automation for stimulus generation. Furthermore, I have contributed to the development of branch predictors, including Alpha and Tage implementations with C++ code. Proficient in System Verilog, UVM, and Python scripting for automation, I am eager to contribute to cutting-edge projects in hardware design verification. I am currently seeking internship opportunities starting from June 2024 and available for 6-9 months, with a keen interest in further advancing my expertise in the field.