Avee Kumar

Background

About Avee Kumar

2 Years of experience in Validation of highly integrated wireless SOCs (System-On-Chip) targeted at Mobile at Qualcomm- Experience in Pre-Silicon Validation on FPGA based HW platforms - Post Silicon Validation with actual Si on HW board based platforms - Silicon bring-up and Debugging - Lauterbach Trace32 -> 6 Months internship experience in Cadence Design, Noida - Designed Modular Fractional Frequency Divider with very low resolution Digital Delta Sigma Modulator - Estimated Systematic spurs level and jitters - Implemented Layout design -> 2 Months internship experience in Cadence Design, Bangalore - Worked on low power, low area D flip flop and Power-On Circuit (POC) cell (Samsung 7nm node)- Wrote test benches for setup, hold, C2Q delay and leakage for D flip flop and power, delay and hysteresis for POC cell on various PVT corners and Monte Carlo simulation on worst case corners- Performed Quality Checks-PERC, Asserts Checks and Floating Gate/Bulk Checks and Reliability simulation (HCI and BTI)- Calculated jitters using Eye-diagram caused by ISI and supply noise with Pseudo Random Binary Sequence -> MTech in VLSI Design Tools and Technology (VDTT) from Indian Institute of Technology Delhi, sponsored by Cadence Design, Bangalore-> Completed BTech in Electronics & Communication from Delhi Technological University (Delhi College of Engineering).