Avinash Chenchala
Senior Design Verification Engineer at Silica Design
Based in Bengaluru, India
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Seniority
Staff
Department
Engineering
Location
Bengaluru
Industry
Semiconductor Manufacturing
Company size
21
Contact information
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a•••••••@silica-design.com
Phone
5 credits+91 ••• •••• ••••
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Background
About Avinash Chenchala
Engineer with focus on IP Verification and VIP development- ASIC/FPGA Verification- Development of AHB VIP from scratch (VIP Architect)- Sub-System Verification which includes Peripherals like Timers, SPI- Test plan / Test case /Test bench development at block level- Hardware Description Languages : Verilog and SystemVerilog- Programming Languages : C - Methodology Expertise : Universal Verification Methodology (UVM)- Simulation Tools : QuestaSim, VCS, NCSIM - Operating System : Linux, Windows. Protocols Having Hands on Experience- AMBA AHB - AMBA APB
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