BASAVARAJ BADIGER
RTL Design and Verification Engineer | Mentor | Educator | Trainer | System Verilog | UVM | Digital Circuit Design | Verilog | SVA | at Semiksha Semiconductor Pvt Ltd
Based in Bengaluru, India
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Seniority
Other
Department
Other
Location
Bengaluru
Industry
Semiconductors
Company size
27
Contact information
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b•••••••@semiksha.com
Phone
5 credits+91 ••• •••• ••••
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Background
About BASAVARAJ BADIGER
• RTL Design Verification Engineer having 2.4 years of experience in IP level/ASIC/SoC Verification. • Well versed with standard protocols such as SPI JTAG AMBA APB AHB-APB Bridge 5G Nb-IoT Rate Matcher Tale bit convolution encoding • System Verilog Verilog Universal Verification Methodology (UVM). Hands-on experience in: • Building UVM based verification environment in System Verilog and UVM from scratch. • Constrain random verification. • Coverage Driven verification. • Assertions. • Test scenario and Test case preparation.
Decision-makers
Other people at Semiksha Semiconductor Pvt Ltd
- SDStaff
Sammed Danolli
Design Verification Engineer · Engineering
- SWStaff
Sneha Wagh
Embedded Software Developer · Information Technology
- KMDirector
Kumarswami Mathapati
Head of Information Technology · Information Technology
- GHManager
Girish Hulamani
Embedded Software Head · Other
- JGManager
Jaya Gudi
Leader · General Business & Management
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