Bert Clewits

Background

About Bert Clewits

I'm an experienced digital as well as a physical design engineer, interested in the design of mixed signal (CMOS) IC's (ASICS) as well as FPGA's From specification upto the final product. I like to work in a multifunctional multicultural/international design team working on new advanced quality products for the future market. my specialties are: VHDL, Verilog/a AMS, known with Cadence, Mentor, Xilinx and Philips design tools,(Synthesis, NCSim, Synopsys) Formal verification. DfT (Design for Test), test pattern generation (AMSAL) Floorplanning, IC place and route tools (SEDSM, PKS),Static Timing Analysis(STA), Clock tree synthesis, IR/power analysis, DRC, LVS, ERC checking, DfM (EMC/ESD), Analog/digital layout creation and matching. Packaging/bonding checking (PARC/PCM). Datamanagement (Temposync/Synchronicity) and third party support/coaching. Bench testing (SAM/ labview).