Bindesh Patel

Background

About Bindesh Patel

Self-motivated, goal-oriented, and highly experienced Design and Verification Tools, Flows, and Methodologies professional with demonstrated success in developing and building Verification Flows, Product Management, and managing top-notch Applications Engineering and Support teams. Recognized for exceptional achievement, successfully driving new products into the marketplace, deep technical competence, communication, organizational skills, and leading closely coordinated team efforts.Areas of expertise: • Solutions Development• Technical Excellence in EDA / CAD Tools• Customer Care / Engagement• Troubleshooting• Low Power (UPF)• PartnershipsKey accomplishments: SOLUTIONS DEVELOPMENT: Developed and deployed unique solutions to check low power rules on customer's designs and UPF for critical violations which cannot be checked by any other technology. TECHNICAL EXCELLENCE: Developed patented new technologies and solutions to drive verification flows that scale with newer designs. CUSTOMER CARE: Led successful engagements with key customers in processor and mobile markets. Provided pre and post-sales support with excellent feedback from all stakeholders. LOW POWER: Led initiative to guide major telecom customer to UPF-based verification and debug flow leading to increased usage and customer success in getting working first silicon.TECHNICAL SKILLS:DESIGN: Verilog, SystemVerilog, VHDL, SystemC, UPF, Synthesis, PrimeTime, SDF, ASIC, FPGA, SoC, SpyGlass.VERIFICATION: MTI, VCS, VCS-NLP, IUS, Verdi, FSDB, Certitude, SVTB, UVM, SystemC, SVA, PLI / VPI, Acceleration, Emulation, Coverage, Static checks, CDC, Low Power.DFT: Full & partial scan, BIST, ATPG, failure diagnosis, fault simulation.TOOLS: Perl, Python, Tcl / Tk, Shell Programming, sed, awk, Linux, OS X, MS Windows, Flexlm licensing, Mediawiki.