Blade Lin

Background

About Blade Lin

Fully understand the ASIC Design / Implementation methodology from RTL to GDSII, and also have EDA tool experiences with various vendors. Cadence →Encounter Digital Implementation System (Place & Route) →NC Verilog →Celtic NDC →Conformal LEC Synopsys →Fusion Compiler / IC Compiler II →Design Compiler →DFT Compiler →Tetra Max →Prime-Time Suit (PX,SI) →STAR-RCMAGMA →Blast Fusion Mentor Graphic →Calibre →MBIST Architect. In charge of ASIC implementation tasks in different stage→Logic Synthesis and constraint definition.→Formal verification.→DFT by scan Insertion.→Memory and ROM BIST.→Physical Design and implementation for emerging process technologies.→Timing analysis and closure.→Power estimation and analysis.→Physical verification.