Bob Waller

Background

About Bob Waller

Senior Hardware validation engineer responsible for end-to-end support of application-specific-integrated-circuits (ASIC). Responsibilities include first time silicon debug, yield analysis and learning, hardware characterization across process / voltage / temperature, quality improvements, customer prototype fulfillment through support of volume manufacturing. Familiar with many aspects of CMOS design methodology ranging from functional verification, design for test, characterization, and failure analysis. Experience with VLSI test equipment, High Speed Serdes macro test, At Speed and DC structural test, memory built in self-test (BIST), ATE pattern debug and data mining using Perl. Excellent problem-solving skills and ability to communicate complex technical issues to product managers, business unit and engineering design leads. Consistently enhanced product development cycle times on projects ranging from embedded CPU’s, Network processors, 5G wireless, and game chips. TECHINCAL SKILLS Highlights • Development and Manufacturing – Support operations, and manufacturing test engineers from first hardware program development to manufacturing qualifications and production. Highlights include first pattern debug success for Logic, Array, and I/O tests. Support product stress and hardware validation for mass production readiness. • Automated Test Equipment – Hands on experience in solving test and design problems using the Teradyne Ultra Flex and J973 test platforms. Performed product characterization shmoo plots to verify design and test pattern stability. • Cadence Encounter Test – At Speed Structural Test, ATPG, Scan and Scan diagnostics, functional patterns, JTAG 1149, Macro Test, Test and Fault coverage analysis • Design – Map embedded Array Built in Self-Test designs to 32nm technology. Performed metric driven verification using System Verilog based testbench and implemented RTL code changes to add bus interface of test control signals, modify address and data logic for targeted memory configurations, and modify clocking logic. • Verification – Test pattern simulation using Verilog RTL and Gate level design models. Interactive debugging and waveform analysis of design issues using Cadence Simvision. Software: • Verilog Hardware Description Language including System Verilog • Perl and Unix shell scripting, R and R studio • ATE programming – Visual Basic, C++. • Operating systems – Unix, Linux, Aix, Windows. Hardware: • Teradyne Ultra Flex and J973 ATE. • Advantest 3340, 6672 ATE. • Digital meters, oscilloscopes, logic analyzers, bench equipment.