Changseok Choi
Soc Design Engineer (Sr Staff) at Synopsys Inc
Based in Gyeonggi, South Korea
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Seniority
Other
Department
Other
Location
Gyeonggi
Industry
Software Development
Company size
28K
Contact information
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c•••••••@synopsys.com
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Background
About Changseok Choi
Experienced in System-on-Chip(SoC) physical design, PSI(EM/IR) and Power analysis with in-depth knowledge of industry leading EDA tools. Especially proficiency in EMIR/power related tools such as ANSYS RedHawk(RHSC)/PowerArtist and Synopsys PTPX. Succeeded many of SoC tape-out as a full-chip power integrity engineer. Also having experience for various foundry services including advanced technology node, such as TSMC(12nm, 28nm, 40nm), Samsung(4nm, 8nm, 14nm) and IFS(10nm). Technical leader of design methodology and sign-off strategy for onchip EMIR and power analysis at the company. I am currently involved in 4nm SoC project and co-working with Samsung foundry design team.
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