Charaka Sai Dinesh

Background

About Charaka Sai Dinesh

Hello, I'm Dinesh Charaka currently working as Design Engineer Intern-Intel. Skills, HDL(Hardware Description Languages)-Verilog. Hardware Verification Language-System Verilog Programming Languages-Python. Scripting Languages-Perl EDA Tools-Xilinx ISE 14.7,Cadence Virtuouso,Model Sim,Quartus Prime. Technical skills-Digital Electronics, Computer Architecture,Analog Electronics,OOPS concepts. Scripting Language-Perl(Basics). Operarting System-Linux, Windows. Co-Curricular Activities- 1.Won 2nd Prize in "Verilog MAKE-A-THON" conducted by VIT Chennai 2022. 2.Participated in "23rd National Conference on Science Engineering and Technology" organized by VIT Chennai. 3.Participated in "24th National Conference on Science Engineering and Technology" organized by VIT Chennai. Project Description, Title-Optimal AES Substitution-Box Construction. Description-Designed an Area Efficient approach of S-Box for Advance Encryption Standard (AES) using Verilog. The optimization resulted in the usage of 17,916 total logic elements, which is less than Conventional model’s 22,445 total logical elements, Area reduced by 4%.