Chuck Seeley

Background

About Chuck Seeley

I'm a Senior Design and Verification Engineer with over 30 years of design and validation experience. My design skills include both front end (Verilog/VHDL coding, simulation, synthesis, and emulation. My verification skills are mostly SystemVerilog based and include the creation of several OVM/UVM class based testbench environments as well as writing both assertion and functional coverage metrics to help in the verification process. Another particular verification area I specialize in is, UPF based low power specification and verification. Over the last 7 years of my time at Mentor Graphics, I was mainly responsible for supporting all of Mentor’s North American accounts in both UPF specification and simulation based debug/verification of many customers low power designs. I’ve used both UPF 1.0 and UPF 2.0 verification flows and I’ve worked with design teams from various companies including Intel, Qualcomm, ARM, Marvell, Cypress, and HGST both in North America and Internationally. I also have extensive experience working in and with multi-site design/engineering teams in the US and abroad. At Siemens-Pyramid, I was the lead designer on a dual MIPS R4400 processor board. I designed all the logic (mainly PLD based) for the CPU complex as well as two separate ASIC's on this board and I also spent time assisting in the floor-planning and layout of the board. At Siemens-Pyramid I also spent time in the lab debugging several boards specifically designed for validating ASIC's using Quickturn emulators. At Micron, I lead an internal project to design and built an in-house emulation board. Using an FPGA partitioning methodology I created and EDA/FGPA tools I picked, we successfully emulated approximately 1.2 million ASIC gates of a 3D graphics chip at 10 MHz. I floor-planned the layout of the emulation board and lead the bring-up and debug of this board.