Corrie Anstey

Background

About Corrie Anstey

Profile : An energetic results driven electrical engineer with 20 years experience in all aspects of hardware design from initial concept through to sustaining. A strong design lead, mentor and team player with superb time management and problem solving skills. Technical Skills : Schematic Design and Layout: · Allegro Design Entry HDL (Concept HDL) user and Allegro layout supervisor · Viewlogic user · Unicad user · Experience designing up to 22 layer boards with Microvia and blind via technology Design Elements: · Multi-core microprocessors (Freescale, Cavium & Broadcom) · Communication technologies (up to10GBase-T Ethernet, 1/10/100Gb optical Ethernet, PCI, PCI-X, PCI-express, PMC, SPI-4.2, LDT, XFI, USXGMII, GMII, RGMII, TBI, USB, JESD, CPRI) · Memories (DDR/DDR2/DDR3 SDRAM, RDLRAM, FLASH) · Power supply circuitry (switching PUPS/POL, LDO) · FPGA/CPLD (board level design)(Xilinx, Altera, Lattice) Simulation · SigXplorer Lab Skills · Lab Equipment (Oscilloscope, Spectrum Analyzer, Logic Analyzer, Multi Meter) · Traffic Generators (Smartbits, Ixia, Innocor) · Optical Test Equipment (Bertscope S, JDSU Hydra 10GbE optical test platform, JDSU ONT-503) · Board level verification and debugging Software Skills · FPGA/CPLD design (Verilog / VHDL, Synplify, Max Plus II) · Documentation (Microsoft Office, Openoffice, Framebuilder)