Daniel Domilescu

Background

About Daniel Domilescu

I am an electrical engineer with 10+ years experience in the semiconductor industry. Currently, I am looking for a full-time position utilizing my design-for-test (DFT) and physical design experience, as well as my personal skills and strengths. My experience has been in design-for-test (DfT) and physical design. I started working with RTL creation and synthesis with VHDL/Verilog of IC modules, RTL design of test control blocks (TCB), and clock control blocks (CCB) to support memory BIST and standards. Throughout my career, I have been responsible for DfT requirements, review and implementation of numerous embedded cores used in Mobile, Home and Automotive applications. Applied complete front-to-back DfT flow on RISC processors (ARM Cortex, MIPS, Tensilica Vectra). Performed synthesis, timing constraints, design strategy and screening, scan insertion, ATPG, testbenches generation, gate-level simulations, design automation and debugging. On physical design part, I have executed several layout benchmarks with ARC family processors in CMOS 65nm and 45nm targeting performance and/or area. Tasks performed: floorplanning, placement, routing, static timing analysis (STA), parasitic extraction and signoff physical verification. My abilities- I am exited to work with new technologies for creating challenging products- I have a strong desire to deliver quality- I am a team player, open, like to share knowledge- I focus on deadlines, customer needs, while I like to explore new possibilities- I have an analytical mind when dealing with issues; Specialties: SKILLS/TOOLS: VHDL,PERL, TCL, TDL (Test Description Language) Scan Insertion/Synthesis: Cadence RC, Synopsys DC DfT tools: Mentor Graphics TestKompress Backend tools: ETS (Encounter Timing System), QRC Formal verification: Formality