Darshan Sarode

Background

About Darshan Sarode

As a VLSI Design Engineer at Silicon Interfaces since August 2022 I have gained extensive exposure to various technologies in VLSI design. I have developed a strong skill set in this field through training in Verilog System Verilog UVM and scripting languages (Shell Python Perl) along with hands-on experience using Tier 1 EDA Tools from Synopsys and Siemens (Mentor Graphics). During my tenure I have successfully implemented protocols such as I2C and I3C conducted fault simulations and got some exposure to high-speed protocol like PCIe. Notably I have contributed to the development of some factions of the Physical Layer of PCIe. Also showcased the advantages of a 64-bit Urdhwa Triyagbhyam Sutra-based Vedic multiplier compared to several other multipliers available in terms of gate count area delay and power consumption. I hold a Bachelor's degree in Electrical Engineering from Pune University and completed a Master's degree in VLSI Design from Vellore Institute of Technology. In my thesis I focused on the implementation and stability analysis of an SRAM cell based on advanced technologies like GAA TFET. Throughout my education and internships I have actively contributed to the VLSI domain with publications in industry journals and presentations at renowned conferences such as DVCon Japan 2023 DAC 2023 Verification Horizon and MPCST IIT Indore. I have collaborated with professionals from top universities both in India as well as Germany to complete Academic as well as personal projects. I also got selected for a research Internship at the Centre for Advancing Electronics Dresden TU Dresden Germany. My goal is to continuously enhance my skills experience the work culture of tier 1 semiconductor companies and contribute to the learning and growth of others as well as myself. I am passionate about mentoring students assisting with academic and placement-related queries and seeking collaborations to gain practical knowledge in VLSI design and verification. Feel free to connect with me for networking collaboration opportunities or discussions in the field of VLSI design and verification.