Davit Babayan

Background

About Davit Babayan

Highly motivated, fast learning Digital IC engineer. 10 year experience of Digital and mixed-signal design in the field of high-speed PHY IPs, STD cells, processors design, etc- RTL design Verilog HDL, writing test bench, RTL and gate level simulation and debugging- Simulation-based functional verification for digital part of USB2,USB3, SATA PCIe using VCS/DVE(Synopsys)- Debugging and fixing mismatches/errors/issues between implemented functionality and functional specification USB2, USB3 PCIe, SATA (test environment, gate-level or RTL issues)- Scan vector generation (ATPG Tetramax), debugging and fixing issues and mismatches- Timing library creation (.lib/.db) for USB and USB I/O's using PrimeTime/NanoTime(Synopsys)- Creating QA flow and running QA for timing libraries- Development, automation, and flow creation for timing library, scan vectors, USB2/USB3/SSP/SATA/PCIe/ regression flows- Experience in working with revision control tools (Perforce)- Flow creation and scripting with languages: TCL, and Perl, Make, CSH- Verilog logic design, synthesis and STA. Tools- Synopsys ASIC: Design Compiler(DC Topographical), PrimeTime, PrimeTime SI, PrimeTime PX, TetraMax ATPG, Formality, Hercules, VCS, Hspice, Nanosim, CosmosSE(LE)- Mentor Graphics ASIC: ModelSim, Calibre - NCverilog/ Verdi Specialties- Digital Design Flow - Logic and Physical synthesis - Functional Verification at RTL and Gate Level- Low Power techniques and Power aware RTL Verification methodology with UPF- Scripting languages: TCL, PERL, Make, CSH,