Debraj Das
Layout Engineer at Texas Instruments
Based in Bengaluru, India
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Seniority
Staff
Department
Engineering
Location
Bengaluru
Industry
Semiconductor Manufacturing
Company size
33K
Contact information
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d•••••••@ti.com
Phone
5 credits+91 ••• •••• ••••
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Background
About Debraj Das
7+ years of industry experience in RF, Analog Mixed-signal, high-speed digital, I/O, STD cell layout and verification. • Worked on 180nm, 65nm, 28nm, 14nm of various foundry technologies. • Experienced in RF layout techniques and finfets. • Knowledge in basic CMOS circuits, matching constraints, design-driven constraints • Good understanding of physical, electrical aspects of layout and Deep Sub micros issues like WPE, STI, LOD, POLY space effects, OD space effect. • Experienced in device matching, signal matching, Parasitic optimization, noise isolations etc • Good understanding of reliability physics including EM, ERC, EOS, ESD and Latchup. • Proficiency with industry-standard layout and verification tools in a Linux environment. • Experience in IP release, on-time execution and swiftly ramping up projects with competent skills. • Possess strong communication, interpersonal, analytical, problem solving and presentation abilities.
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