Deepak Namana
Soc Design Engineer at Intel
Based in Andhra Pradesh, India
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Seniority
Staff
Department
Engineering
Location
Andhra Pradesh
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
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d•••••••@intel.com
Phone
5 credits+91 ••• •••• ••••
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Background
About Deepak Namana
CAREER OBJECTIVE Looking forward to work on challenging tasks where I can put my skills to maximum use and sharpen my capabilities that help me achieve personal as well as organization goals. PROFESSIONAL SUMMARY Worked on N5, N7, 28nm, TSMC 40nm, TSMC 90nm and 130nm technology nodes. Handled partitions with instance count ~2.8M. These partitions go into complex networking subsystem RDMA. These are congestion, LOL & Fanout critical partitions. Handled CPU partition which has Cadence Xtensa core and runs at 1.2GHz @ 0.675V Worked on chip level activities which includes IO & Bump placement and Analog custom routings. Dealt with blocks having floorplan critical & routing congestion and Clock Tree Balancing issues. Responsibilities were doing sanity checks, floor planning, placement issues, balancing clock tree based on timing issue, routing issues, STA, EMIR and LV checks. SKILS Tools: Fusion Compiler, ICCII, ICC & PT. Scripting Languages: TCL
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