Dharmesh Bhakta

Background

About Dharmesh Bhakta

Silicon Validation Engineering Leader & Principal Engineer with 20+ years in post-silicon validation of high-speed memory IP — DDR5, LPDDR5, DDR4, LPDDR4, HBM2E, and custom PHY & I/O — across FPGA, ASIC, and structured ASIC product lines at LSI, Broadcom, Intel PSG, and Altera. Known for staying hands-on in the lab — bench bring-up, probing, debug scripting, and triaging silicon failures. What I Do: Architect and lead end-to-end post-silicon validation strategies — from shift-left planning through volume validation into PRQ — targeting marginality, test-to-fail, interoperability, and scalability. Led RevA/NPI power-on bring-ups / teams for AgileX (10nm), PCIeGen5/CXL, Stratix10 (HBM2), eASIC, and DDR5/LPDDR5 portfolios across multiple GEOs.Debug Lead: Dispositioned hundreds of sightings across FW, SW, HW, and platforms on Arria10, Stratix10, and AgileX. Led task forces across GEOs on low-DPM failures across DDR5, LP5, DDR4, HBM, and IO — covering multi-rank calibration, fmax to 6400Mbps+, V/T drift, and RDIMM PMIC/RCD calibration. Developed debug playbooks, stress-to-fail methodologies, and multi-site 24hr debug strategies.Validation Architecture: Developed ground-up validation plans and PVT strategies for memory IP (PHY, I/O, Controller, Firmware, Traffic Generators). Defined landing zone requirements, risk-based test coverage, solution space randomization, and shift-left activities including emulation tasks, HW/FW simulations, and DFD/BIST use-cases.Platform & Board Architecture: Defined memory interface topologies across 50+ channels, 20+ platforms, and 100+ BOM permutations for DDR5, LPDDR5, HBM2E, DDR4, and LPDDR4 — schematic through layout including power sequencing, SI constraints, debug accessibility, and lab bring-up readiness.Technical Depth: Memory PHY, I/O, Controller & Firmware | SI (IBIS, HSpice)| Board Design (Cadence Allegro)| Automation (Python, Perl, TCL, LabVIEW)| Statistical Analysis (JMP)| Lab Equipment (Logic/Protocol Analyzers, Scopes)Highlights: · 3 U.S. patents: DDR bit-error testing, high-speed multi-interface I/O, self-refresh memory control· 8 internal publications: HBM2 power-on, DDR4/5 analog validation, PDN noise, FPGA validation frameworks · Intel DRA Awards: First FPGA+HBM2 demo ahead of competition, first 10nm AgileX bring-up, RNR EAP in 7 days · DCAI Culture Hero Award (Q3'21) — fearless cross-BU leadership across Intel's post-silicon ecosystem Passionate about high-performance validation teams, AI-assisted debug, and pushing silicon quality at the leading edge. Dublin, CA