Diptesh Datta

Senior Asic Engineer at Nvidia

Based in Hyderabad, India

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Seniority

Staff

Department

Engineering

Location

Hyderabad

Industry

Computer Hardware Manufacturing

Company size

45K

Contact information

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Email

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d•••••••@••••••.com

Phone

5 credits

+91 ••• •••• ••••

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Background

About Diptesh Datta

Accomplished VLSI Professional | Senior ASIC Design Engineer at NVIDIA | 3+ Years Experience Expertise: • Proficient in digital logic design, Verilog, LINT, and Clock Domain Crossing and Reset Domain Crossing Analysis for robust logic optimization. • Strong grasp of RTL Design, simulation-based flows, with a knack for debugging and creative problem-solving. • Proven track record in identifying and resolving complex technical issues, offering innovative solutions. • Proficient in crafting comprehensive micro-architecture documents, translating high-level concepts into functional designs. • In-depth knowledge of SoC, Semiconductor Memory, and Cache architecture concepts. Prior work experience: • I have previously worked as a Design Engineer in Micron's NAND team, focusing on digital design and verification for the next-gen 3D-NAND Flash QLC and TLC Memory. In addition to design tasks, I implemented Assertion coverage-based verification techniques within the White Box Design Validation (WBDV) Environment to guarantee compliance with timing and performance standards. My duties also encompassed post-Silicon verification and debugging for ongoing projects, involving close collaboration with cross-functional teams in design, verification, device, and product engineering, from the US, Italy and Singapore. Academic Background: • M.Tech in Electrical Engineering, specializing in Microelectronics and VLSI Design (2020) from Indian Institute of Technology, Gandhinagar. • M.Tech Thesis:"Application-Centric Efficient SRAM/CAM/TCAM Memory Design," showcasing innovative designs in Content Addressable Memory (CAM), Ternary CAM (TCAM), and Static Random Access Memory (SRAM) for robustness, energy-efficiency, and high-speed operation. • Was a recipient of Travel Funding from IIT-GN for presenting a research work at the 15th International Conference on Electron Devices and Solid-State Circuits, Xi’an, China (June 2019). Open to professional engagements and networking opportunities in VLSI, ASIC Design, and semiconductor-related domains.

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