Dragan Stancic
Senior Analog Asic Layout Engineer at Elsys Eastern Europe
Based in Serbia
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Seniority
Other
Department
Other
Location
Serbia
Industry
Semiconductor Manufacturing
Company size
125
Contact information
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d•••••••@elsys-eastern.com
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Background
About Dragan Stancic
Analog and mixed signal IC layout engineer. Leading the projects with complete IC layout solutions from schematic / requirements, size and area estimation, ESD-IO Padring, floor-planning, module level (IP) and top level planning, generation and verification; chip finishing, packaging and MBD generation, density, antenna, ESD, DFM etc. Auto-routing of digital signals on the chip. Working in analog technologies from 500nm down to 7nm FinFET. Working on layouts for high power, ultra low power applications in base-band and RF, wireless, automotive, home and performance critical applications. Working on Power management, Audio, Air-bag, micro-controller, driver, RF transceiver and DC\DC converter chips. K2, Assura, PVS and Calibre verification tools, Cadence tools (VLE, VXL, GXL) for layout generation and verification (IC6.1.8). SKILL for Cadence understanding and coding. Basic shell and Perl scripting.
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