Faiza Khan

Staff Layout Engineer at Arm

Based in Bengaluru, India

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Seniority

Staff

Department

Engineering

Location

Bengaluru

Industry

Semiconductor Manufacturing

Company size

12K

Contact information

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Email

1 credit

f•••••••@arm.com

Phone

5 credits

+91 ••• •••• ••••

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Background

About Faiza Khan

About 10 years of Working experience across various aspects of memory layout development covering multiple blocks eg.mux cells, decoders, memory control, sense amplifiers etc.• Worked on various Technologies that includes 2nm 3nm 5nm Finfet, 28nmFDSOI, apart from CMOS planar bulk Technologies 22nm, 32 nm, 40nm, 130nm and 180nm nodes.• Involved in all aspects of memory compiler Development including floorplanning and planning of power supply on critical nets, Leafcell development, layout Tiling, Signal Continuity and signal flow robustness, netlist stitching.• Good Understanding of memory design including bitcell, sense amp, decoders, and I/O• Verification capabilities which includes DRC, LVS, DFM, ANTENNA,Density,LefCheck,ERC,EM/IR, Latchup Effects Well Proximity,Shielding.• Proficient in various development and verification tools like Virtuoso, Calibre, Synopsys Custom Compiler, TOTEM, Star RC, Voltus-fi etc.• Basic Knowledge of cadence skill coding and shell scripting.• Concise understanding of logic design and CMOS concepts.

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