Fatemeh Negin Javaheri

Background

About Fatemeh Negin Javaheri

Detail-oriented and self-motivated RTL Design Engineer with over 15 years of academic and industrial experience in FPGA digital circuit design and verification- Specialized in managing the entire design process, from specification definition to final product validation- Proven track record of creating high-performance and efficient designs for complex systems-on-chip (SoCs)- Experienced in ensuring high-quality deliverables through simulation-based and formal verification, developing and executing comprehensive verification plans, and automating test environments- Hands-on experience in assertion-based verification- Experienced in using UVM to create robust verification environments that enhance productivity and quality- Demonstrated ability to collaborate with cross-functional teams to deliver innovative solutions, ensuring design reliability and functionality through rigorous verification methodologies- Strong problem-solving skills and attention to detail for tackling challenging design issues- Excel in providing thorough documentation and technical collateral to customers- Proven ability to manage projects from initiation to completion, ensuring high-quality deliverables. Familiar with Agile methodologies and tools like Jira for effective project planning- Committed to continuous learning and staying current with industry trends, thriving in dynamic environments that foster cutting-edge technology development.