Federico Goller

Background

About Federico Goller

After my graduate studies in Electronic Engeneering (topic: new vector/DSP CPU architectures for video algorithm processing, final grade 110/110 cum laude), I have been working as a freelance on R&D and digital HW design. During my job in Atmel Roma, I designed a multi-core (ARM+DSP) SoC; I conducted all the front-end steps (RTL design, documentation, synthesis, DFT insertion) and I have been deeply involved in the PnR implementation steps.Past experiences cover System-C RTL-TLM modeling, Matlab/Simulink system simulation, embedded programming in assembler/C.I worked, for Pegasus MicroDesign, on the Block-Level and System-Level verification of SystemC/VHDL/Verilog IP for automotive applications, for Bosch and STMicroelectronics.From 2011 I have been working as Digital Design Architect Engineer for STMicroelectronics (automotive), on the architecture definition and RTL design of AMBA based sub-systems (ARM Cortex cores/interconnect//memory subsystem design, AXI/AHB/APB bridges design); eNVM controller design; Safety architecture definition and safety mechanisms implementation like e.g. e2e ECC, customized lockstep and split-lock for the cores and peripherals.More recently I have been working as a design leader and architect on multicore ARM based automotive SoCs.From 2021 I have been working as architect and technical leader in an ASILB multicore SoC with security for Monolithic Power Systems. I have ownership on the SoC high level specifications (including safety and security architecture), digital design of many system IPs (AMBA) e.g. bridges memory controllers (eFlash and RAM ) system MPU, DMAC, and analog design and backend phases supervising.From September 2022 I have been working as Senior Staff Engineer in SiFive, in FuSa aware design at core level and system level. Specialties: Verilog/SystemVerilog/VHDL SoC and IP design, Architectures, Bus protocols (AMBA AXI, AHB, APB),Functional Safety,Synthesis,Embedded C programming