Gabriel Caffarena

Background

About Gabriel Caffarena

R&D Manager: Open RAN, ASIC, FPGA, 5G. 25-year at universities: UCL, Imperial College, Oxford, INSA-Rennes, UPM, USP-CEU. Research: approximate computing, low-power design VLSI/FPGA and MCU systems, FPGA/GPU acceleration of algorithms (DNN, Neuroscience, ECG, Electron Microscopy, Bioinformatics, etc.), embedded C and ARM assembly. Author and co-author of 90 publications VLSI, ACM FPGA, ISCAS, FPL, TCAD, TCAS-II, Int. J. of Electronics, IET Circuits and Devices, etc.) with 900 citations. Four patents on digital systems. More than 20 R&D projects. Research visitor at University of Oxford, Imperial College, IMEC. Invited Professor at INSA-Rennes. University teaching: Profesor Titular accreditation, Coordinator of Master in BIomedical Engineering (USP-CEU), Quality Assurance Committee member (USP-CEU), Lecturer in Random Signals, Parallel Computing, Digital and Analog Electronics, Digital Systems, Digital and Analog Communications, Computer Architecture, Telecommunication Systems, etc. CUDA, VHDL/FPGA and Matlab training. Senior Member. Chair of the EURASIP Seminar on Hardware Design of DSP Systems (2010-2016).