Gamini Anil Kumar

Background

About Gamini Anil Kumar

12+ years of hands-on experience in RTL-GDS Flow including CAD/Methodology Development, FullChip flows, PnR, STA, and Physical Verification. • Block-level Lead for FPGA chip in 7nm, Networking Device SoC & its successor in 7nm, IoT chip & its successor in 22nm, Server chip for 40nm, Hearing Aid device in 40nm. • Deployed various Methodologies like Multi-Scenario Timing in PT, PG RDL Generation, Clock-Tree Implementation, PnR Optimization sequence, PG mesh methodology etc. • Closely worked with EDA Vendors for better PPA in lower nodes to achieve fine balance b/w QoR, Runtimes. • Developed sophisticated and robust CAD infrastructure for entire Physical Design Flows for both block-level, Full-Chip cycles which includes Syn, PnR, ECO, FCI, FCT, Physical Verification, RDL Generation and IR/EM Analysis which is a push-button flow with initial User Inputs. • Implemented Full-Chip tasks like FloorPlanning, Partitioning, Pin Placement, Budgeting, PnR, Full-Chip Timing etc and attained better QoR in terms of Area, Channel Estimates, congestion less routing etc. • Handled PnR, STA and ECO for wide variety of blocks (ranging from 200k to 8M inst count) in 7/22/28/40/65/180 nm technologies and succeeded in providing better QoR.