Hemant Chawla

Background

About Hemant Chawla

OBJECTIVE:Intend to work as a key player in leading corporate of high tech environment in field of VLSI design and verification, where I can explore myself and utilize my potential.SKILL SET- Language: C, C++, HDL, VHDL, Verilog, SystemVerilog- Verification Methodologies: OVM, UVM- Bus Protocols: PCI Express Gen1/Gen2/Gen3/Gen4/Gen5/Gen6- Simulation Tools Used: Model Sim, VCS, NC Verilog- Debugging Tools Used: Verdi, DVE, Simvision- Platforms: MS-DOS, Windows 98/XP/VISTA/7/10, Linux - Repositories: SVN, Perforce, GIT- Computer Exposure: MS Word, MS Power Point, MS ExcelAREAS OF EXPERTISE- Understanding the complete flow and architecture of different tiles within a sub-system- Creation of passive verification components (bus monitor) from scratch in UVM- Creation of verification environment, high-level modelling based on Verilog- Experience of block level verification- Good specifications understanding of PCIe Gen1/Gen2/Gen3/Gen4/Gen5/Gen6 and PCIe PIPE 3.0/4.0/4.2/4.3/4.4/5.1/5.2 protocol- Code maintenance of Verification Suite, implementation of new enhancements and bug fixing- Requirement Gathering and Clarifications- Preparation of Test Plans and Functional Documents- Coding and execution of Test Cases in Verilog and System Verilog (OVM/UVM)- Timely support to the customers- Integration and creation of new environments- Supporting client interaction for the evaluation and execution of the product and bug fixing- Clear understanding of domain, language and tools used in the protocol- Writing articles/blogs related to PCIe to help customer resolve their queries and get knowledge about the different sections of PCIe protocol- Involved in release packaging, regression and validation- Involved in documentation work i.e. updating User Guide, Release notes, etc