Hoon Ser
Principal Design Engineer at Asml
Based in San Jose, United States
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Seniority
Staff
Department
Engineering
Location
San Jose
Industry
Semiconductor Manufacturing
Company size
36K
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h•••••••@asml.com
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Background
About Hoon Ser
Research Experience : 1. EUV Lithography, RET, SMO - EUV patterning - EUV source optimization for low variability, low pattern shift 2. DTCO - Beol patterning strategy - Patterning budget and variability study 1. Computational Lithography (OPC, RET)- OPC setup for DRAM and Logic device - RET, Model, Recipe, Etch skew - Rigorous Litho simulation 2. Photo Lithography - Device layer setup (FEM setup, Hot spot inspection)- Precise and extensive Measurement by CD SEM 3. Design-Technology Co-Optimization (Design rule)- Logic device Patterning Design Rule suggestion and assessment - Process assumption review 4. Semiconductor Laser and LED Technology (at Opticis)- GaAs Laser : fabrication and characterization - Laser and LED packaging
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