Isaac Peterson

Sr Systems and Applications Engineer at Astera Labs

Based in Santa Clara, United States

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Seniority

Staff

Department

Information Technology

Location

Santa Clara

Industry

Semiconductor Manufacturing

Company size

944

Contact information

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Email

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i•••••••@asteralabs.com

Phone

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Background

About Isaac Peterson

Currently working on Astera Labs Aries line of PCIe and CXL retimers. I'm focusing on system validation testing with root complexes from Intel, AMD, and new player Ampere, as well as endpoints from across the ecosystem. Plenty of hardware and firmware debug to ensure everyone is playing by the rules and we're reaching our goal at Astera Labs: eliminating connectivity bottlenecks in Data Centric Systems. As Astera Labs grows, there's high potential for wearing several hats. I'm also directly involved with our great team of Field Applications Engineers to assist in customer issues encountered when integrating our retimers into their systems. We have high visibility in Silicon Valley with our team in Santa Clara, as well as great representation with our teams in Shanghai and Taipei. Astera Labs has been a great home for me for the past seven months, and I hope to support this team for years to come.

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