Jack Z. Lin

Background

About Jack Z. Lin

S’95-M’99 & 01) MS in ECE with 10+ years Mixed-Signal IP design, verification and integration industry experience in Silicon Valley. Thorough understanding of integrated circuit CMOS design & layout techniques, as well as FINFET process technologies. Go through several product cycles and the silicon went into volume production for several customers in wireless, storage and wireline communication application. Fully understanding of RX-ADC, TX-DAC, LO-PLL and DC-IVF design, verification, integration and layout with significant cell level experience optimized of power, circuit performance and layout area for different application in the different process nodes from 0.35um to 5nm. Experience with design and verification tools (Cadence Virtuoso IC design environment, Analog circuit simulation tools like SPECTRE, HSPICE, FINESIME, Layout verification tools like Caliber, Layout parasitic extraction toolset). A background includes scripting and programming languages which include Python, C etc. Understand how to model analog circuit behaviors using circuit abstraction tools like MATLAB, Verilog-AMS etc. Class training of Verilog and System-Verilog. Hand-on experience in using spectrum analyzers, oscilloscopes, signal generators, DC meter and network analyzer etc. to validate analog designs. Experience in working with test engineers for yield improvement and design for testability issues. Clear and effective communication. Concise and detail documentation. Career interest includes analog, RF and Mixed-Signal IP design, verification and integration for Monolithic CMOS transceivers for Wireless & Wireline communication application.