Jacob Levin
Verfication & Fpga Rtl Design at Verisense
Based in Israel
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Seniority
Staff
Department
Other
Location
Israel
Industry
Semiconductors
Company size
18
Contact information
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j•••••••@verisense.com
Phone
5 credits+972 ••• •••• ••••
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Background
About Jacob Levin
I have a lot of experience in ASIC/VLSI design, most of my designs were involved in communication systems as packet switching, SONET/SDH and wireless communication. My experience in ASIC/VLSI design is spread on all levels of the design- Architecture - Logic design (Verilog and VHDL)- Full custom- Standard cell - FPGA - Verification I like to enter and learn new fields. In my free time I love to ride my mountain bike, prepare and lead long bike rides, then share it with others. Some of my rides you can see in the following link (Sorry, this is in Hebrew only): http://rechasim.com/gps/routes.htm
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