Jakub Cabal

Background

About Jakub Cabal

I am an FPGA engineer specializing in high-speed network traffic processing, with expertise in 400G Ethernet and PCIe Gen5 interfaces. I have been working at CESNET since 2014, transitioning to a full-time position in 2017. I currently lead a small team of FPGA developers, pushing the boundaries of FPGA technologies to achieve cutting-edge performance. A key milestone in my career is the implementation of a high-speed packet DMA controller capable of 400 Gbps throughput, along with optimizing FPGA designs for low latency and high efficiency. Our solutions contribute to enhanced data processing in modern high-performance network infrastructures. I have published my work several times at leading FPGA conferences, sharing insights and contributing to advancements in the field. In addition to technical development, I lead my team and mentor junior engineers.