Jan Grabinski

Background

About Jan Grabinski

Motivated, resourceful and innovative Analog/Mixed Signal Engineer. With three patents filed for Synopsys. Always eager to face new challenges and to bring novel solutions- Hands-on experience in Analog/Mixed Signal full custom high speed (up to 6Gbps) circuitry design from specification to working silicon- Hands-on experience with plenty of PLLs and DLLs architectures (double charge-pump, self-biased [Maneatis], double loop, PI loop, loop with swallow divider, fast lock, low bandwidth OTA loop, ultra fast locking DLL etc.)- Basic power management design (bandgap voltage references, regulators etc.)- Design flow preparation and implementation- Participation in system and design reviews - Chip debugs- Junior designers coaching- Development of circuits for world leading technologies (65nm down to 14nm; TSMC, UMC, GF etc.)- Willing to learn and acquire new skills- Flexible- ready to meet stringent deadlines with high quality products. Experience with following EDA tools: HSpice, FineSim, XA, HSIM, Galaxy Custom Designer, Wave Viewer, CosmosScope, Saber, Cadence Virtuoso, VCS. Known programming/modeling languages/tools: Matlab/Simulink, Verilog-A, Verilog, VHDL, C, C++, TCL, Unix scripting.