Jan Michael Espinosa

Background

About Jan Michael Espinosa

Semiconductor Engineer I specialize in custom layout design for both digital and analog cells, with the ability to work independently while ensuring high-quality results. I am highly skilled in debugging and resolving Design Rule Check (DRC) and Layout Versus Schematic (LVS) issues, leveraging the latest technologies and a range of architectures.My experience includes designing layouts from scratch, starting with device placement and signal flow considerations, and extending through routing base layers up to the covercell level. I am adept at interpreting and analyzing device schematics, making necessary manipulations within the constraints and guidelines provided.In addition, I have hands-on experience with memory and interface projects. My flexibility allows me to adapt to various architectures, ensuring compliance with the specific Design Rule Manuals (DRM) of each technology.Proficient in CAD tools used for IC layout design, I am also well-versed in troubleshooting and debugging tool-related issues to maintain efficient design processes.