Janarthanan Narayanan
SOC design engineer at Aeva at Aeva
Based in Bengaluru, India
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Seniority
Other
Department
Other
Location
Bengaluru
Industry
Automotive
Company size
292
Contact information
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j•••••••@aeva.com
Phone
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Background
About Janarthanan Narayanan
Result oriented focused technically well equipped and resourceful with proven ability in Front-end RTL Design. Expertise in RTL Design synthesis simulation Lint CDC STA support. Worked on Memory protocols like DDR5 DDR4 RLDRAM3 HBM3 GDDR6 IP. Expert in DDR4/5 protocol. Worked on DFI 4.0/5.0 interface protocol. Developed complex DFI BIST useful for memory vendors for DDR4/5. Supported verification and physical design team. Worked on DDR4 bring up activities. Worked on Emulation/Prototyping of DDR4 memory with Xilinx FPGA. Worked on VHDL Verilog System Verilog Xilinx/Actel FPGA Xilinx Vivado flows Cadence genus.
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