Jason Luu

Background

About Jason Luu

I fell in love with the world of FPGA software in 2005 and never looked back since. The problems are deep and engaging. Advances in the field visibly impact real people and the real world. Those who join tend to become quite passionate about their work, some even continue to make contributions after retirement. This unique combination of challenging technical problems and fantastic colleagues makes for a great field to work in. Today, my team works on advanced timing analysis and design optimization in Intel's Quartus FPGA compiler to help hardware engineers solve various kinds of timing problems in their FPGA design. In the past, I've touched many parts of FPGA CAD. In industry, I've worked on subjects such as routing, incremental compilation, clustering, power modeling, and customer design closure. In academia, I worked on open source FPGA tools (VTR), which eventually got used by Texas Instruments, Efinix, and other companies. Outside of software, I've worked on an FPGA accelerator for Princess Margaret Hospital for cancer treatment planning. Outside of FPGAs, I've led technical projects on various parts of the software stack for new compute chips at Intel.