Javeed Shaik
Layout Design Engineer at Altran
Based in Hyderabad, India
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Seniority
Staff
Department
Engineering
Location
Hyderabad
Industry
Information Technology and Services
Company size
12K
Contact information
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j•••••••@capgemini-engineering.com
Phone
5 credits+91 ••• •••• ••••
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Background
About Javeed Shaik
Working as Analog and Mixed signal Layout Engineer in the Semiconductor industry delivering quality work.Hands on experiences in 2nm, 3nm (TSMC), GAAFET(INTEL), 7nm, 10nm, 14nm technologies.Layout tools : Cadence - Virtuoso & genesys.Physical verification : LVS, HV, DRC and other (PROD) bundle flows.RV tool : Totem (IR & EM).Worked on Assembly Test Technology Development (ATTD)/Embedded Multi-Die Interconnect Bridge (EMIB) layout design projects.SKILL SET:Worked on Analog/Mixed signal Layouts.Strong understanding towards floor planning, Signal Flow, Shielding, Matching techniques, LVS verification and debugging.Well Versed with all the verifications till tape out including LVS, DRC, RV, ANTENNA, LATCH UP and Matching of devices, Shielding and Parasitic Extractions.Good knowledge in Analog layout design, CMOS fabrication, Layout issues.Good at UNIX and shell scripting.
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