Jay Trivedi

Background

About Jay Trivedi

As the Director of Engineering for Silicon Design at Edgecortix, I lead all facets of ASIC and IP SoC Design and verification efforts. My role encompasses the entire project lifecycle, from Statement of Work (SoW) through Tapeout & Board design. A key achievement includes spearheading the verification, integration, and coordination with external physical design vendors, which directly led to the successful tapeout and successful bring up of Sakura Chips. My hands-on experience in chip bring-up and board design has been instrumental in executing these complex projects. I've established and managed robust verification environments from scratch, leveraging UVM, Verilog, and System Verilog. My technical expertise extends to developing comprehensive verification infrastructures using industry-standard tools like Xcellium, Vivado, and Spyglass Lint, alongside proficiency in Perl, TCL, and Python scripting. I'm adept at debugging RTL, simulations, and synthesis/place-route issues, maintaining rigorous oversight of IP releases to ensure top-quality standards. Beyond technical leadership, I possess strong negotiation and relationship-building skills. I've cultivated impactful partnerships with various IP and EDA tool vendors, significantly contributing to company success. My effective communication skills have been pivotal in opening new business avenues and securing beneficial deals, particularly for the startups I've worked with. I thrive in high-pressure environments, consistently demonstrating an ability to multitask and drive innovation and excellence within the semiconductor industry.