Jeff Allgood

Background

About Jeff Allgood

I have recently accepted a position with Silanna Semiconductor as a Technical Design Engineering Program Manager and look forward to working with the engineering team there. I start there at the end of October, 2023. Prior to that, I worked for AMI / AMIS / ON Semiconductor / onsemi for over 22 years. For the past 17 of those years, I have been a technical lead for custom ASICs and ASSPs leading teams of 2 - 12 people. This includes being responsible for all technical documentation for specifications, verification, validation and the qualification for each projects. I started as an analog design engineer for AMI Semiconductor after graduating from the University of Utah in 2001. I worked concurrently on my Masters of Engineering from the University of Idaho for the next three years. During that time AMI became the publicly traded company AMIS. AMIS was then bought by ON Semiconductor in 2008. ON Semiconductor was recently rebranded as onsemi. During the 22 years as a Mixed-Signal design engineer, I have been promoted 6 times and have consistently been a top performer in my engineering teams. I currently hold the position of Senior Principal Design Engineer. I have experience in designing a wide range of circuits such as operational amplifiers, comparators, bandgaps, regulators (linear and switching), SAR ADCs, pipeline sigma delta ADC, switched capacitor filters. gain amplifiers, sample and hold circuits for multiple ADC inputs in the pipeline ADC, High Voltage drivers and support circuits such as level shifters for BLDC motors up to 140V. Along with design, I have extensive layout experience at cell, block, and chip levels primarily using Calibre in a Cadence Design Environment. I also have extensive chip level mixed signal simulation experience. This includes designing and using systemVerilog real number models for modeling analog blocks and simulating with digital RTL and gate level synthesized digital blocks. My favorite part of my job has been the interaction with the other engineers within and outside of my organization and being able to learn from and collaborate with them.