Jerin Jacob

Background

About Jerin Jacob

I have over 15 years of expertise in FPGA IP and SOC Verification. Having worked with Xilinx for close to a decade I was responsible for verification and addition of Video Standard IPs in Vivado IP catalog. I have domain knowledge of HDMI 2.1/2.0/1.4, SMPTE UHD - SDI, SMPTE 2022, H264 Codec, AMBA AXI, AHB bus protocols. I have experience of complete verification flow starting from Testplan & Testbench creation, Testcase, Assertion and Cover point writing, Netlist Simulation, Coverage Closure across multiple projects. I have developed testbench Infrastructure using System Verilog and UVM Methodology and automated regression scripts using shell, python scripting language. For last couple of years I have additional responsibility of Verification Team management which includes the tasks of Project planning, progress tracking and timely delivery.