Jerrin Joseph
Senior Engineer at Qualcomm
Based in Bengaluru, India
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Seniority
Staff
Department
Engineering
Location
Bengaluru
Industry
Semiconductor Manufacturing
Company size
58K
Contact information
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j•••••••@qualcomm.com
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5 credits+91 ••• •••• ••••
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Background
About Jerrin Joseph
ASIC-SOC Design Engineer (Contractor )SanDisk India Device Design Pvt Ltd- Bangalore, India (February-2017 to present)Key Duties- Part of ASIC Development team- Working in designing Memory controllers for USB and SSD’s- Experience in CDC checks using meridian cdc- Experience in LINT - Experience in LEC checks using formality- Experience on UPF development, Multi-Voltage Rule Checks of SSD controller- Completed VLSI Front end Design and Verification training at Maven Silicon, Bangalore- Completed M.Tech from NIT Trichy in Process Control and Instrumentation- Actively seeking internships or Co-op / Full-Time opportunities in VLSI domainTechnical Skills:Design : RTL Design, Gate Level Design, Synthesis. Design Tools : Xilinx ISE, Ascent lint, meridian cdc, formality, conformal, ncverilog, simvisionHDLs : Verilog.HVLs: System Verilog Others : Adobe, Microsoft Word, Excel, PowerPoint- Interested in RTL Design, Digital Circuit Design, ASIC Design, SoC Design.
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