Joep Boonstra

Background

About Joep Boonstra

Driving hardware and hardware/software architecture definition for IP in the domain of AI, machine learning and Digital Signal Processing- Translating customer requirements into innovative products and IP solutions- Leading and coaching multi-site teams, developing state-of-the-art IPs, SoCs and subsystems- Hand-on attitude, leading by example - Strong background in design and verification processes and methodologies - Long history of successful products, including the Synopsys NPX, EV, and EM DSP family - 30+ years of experience in multiple domains ranging from NPU/CPU/DSP architecture and EDA tool development to GDS2 and tape-out. Skills- Technically coordinating and coaching multi-site projects across Asia, Europe, America, Africa, including multi-year expat experience in SE Asia - Taking ownership, time-to-market, delivering on commitments - Complex IP design: AI, Convolutional Neural Networks, Internet of Things, Automotive, CPU/DSP micro-architecture, performance analysis, low-power- Leading NPX, EV and ARC DSP: specification, micro-architecture, CNN, DNN, SIMD, DSP ISA, low-power, FuSA - IP quality, leading design process improvement initiatives - DSP applications: audio, voice, vision, sensors, IoT - L2 caches and DDR(2/3), LPDDR(2) memory controllers, Ethernet, PCIExpress - Synopsys, Cadence tools - SystemVerilog, Verilog, SVA, UVM, SystemC/C modelling